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PRELIMINARY TECHNICAL DATA
=
16-/32- Channel, 3.5 1.8 V to 5.5 V, 2.5 V, Analog Multiplexers ADG726/ADG732 Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAMS
ADG732
S1 S1A DA S16A D
FEATURES 1.8 V to 5.5 V Single Supply 2.5 V Dual Supply Operation 3.5 On Resistance 0.5 On Resistance Flatness Rail to Rail Operation 30ns Switching Times Single 32 to 1 Channel Multiplexer Dual/Differential 16 to 1 Channel Multiplexer TTL/CMOS Compatible Inputs For Functionally Equivalent devices with Serial Interface See ADG725/ADG731 APPLICATIONS Optical Applications Data Acquisition Systems Communication Systems Relay replacement Audio and Video Switching Battery Powered Systems Medical Instrumentation Automatic Test Equipment
ADG726
S1B DB S32 WR CS S16B WR CSA CSB
1 OF 32 DECODER
1 OF 16 DECODER
A0 A1 A2 A3 A4 EN
A0 A1 A2 A3 EN
GENERAL DESCRIPTION
The ADG726/ADG732 are monolithic CMOS 32 channel/dual 16 channel analog multiplexers. The ADG732 switches one of thirty-two inputs (S1-S32) to a common output, D, as determined by the 5-bit binary address lines A0, A1, A2, A3 and A4. The ADG726 switches one of sixteen inputs as determined by the four bit binary address lines, A0, A1, A2 and A3. On chip latches facilitate microprocessor interfacing. The ADG726 device may also be configured for differential operation by tying CSA and CSB together. An EN input is used to enable or disable the devices. When disabled, all channels are switched OFF. These multiplexers are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance and leakage currents. They operate from single supply of 1.8V to 5.5V and 2.5 V dual supply, making them ideally suited to a variety of applications. On resistance is in the region of a few Ohms and is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either Multiplexers or De-Multiplexers
and have an input signal range which extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break before make switching action preventing momentary shorting when switching channels. They are available in either 48 lead LFCSP or TQFP package.
PRODUCT HIGHLIGHTS
1.
+1.8 V to +5.5 V Single or 2.5 V Dual Supply operation. These parts are specified and guaranteed with +5 V 10%, +3 V 10% single supply and 2.5 V 10% dual supply rails. On Resistance of 3.5 . Guaranteed Break-Before-Make Switching Action. 7mm x 7mm 48 lead LF Chip Scale Package (CSP) or 48 lead TQFP package.
2. 3. 4.
REV. PrD 2001
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2001
PRELIMINARY TECHNICAL DATA
ADG726/ADG732-SPECIFICATIONS1(V
Parameter ANALOG SWITCH Analog Signal Range On-Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION
2
DD
= 5V 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
B Version -40C +25oC to +85C 0 V to VDD 3.5 5.5 6 0.3 0.8 1.2 0.01 0.5 0.01 0.5 0.01 1
Units V
Test Conditions/Comments
0.5
typ max typ max typ max typ max typ max typ max
VS = 0 V to VDD, IDS = 10 mA; Test Circuit 1 VS = 0 V to VDD , IDS = 10 mA VS = 0 V to VDD, IDS = 10 mA VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 3 VD = VS = 1 V, or 4.5V; Test Circuit 4
5 5 10 2.4 0.8
nA nA nA nA nA nA
V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ pF typ pF typ pF typ pF typ pF typ A typ A max VIN = VINL or VINH
0.005 0.1 5 40 60 30 1 32 50 10 14 5 -60 -60 10 13 180 360 200 400 10 20
Break-Before-Make Time Delay, tD tON(EN, WR) tOFF(EN) Charge Injection Off Isolation Channel to Channel Crosstalk -3 dB Bandwidth C S (OFF) C D (OFF) ADG726 ADG732 CD, CS (ON) ADG726 ADG732 POWER REQUIREMENTS IDD
RL = 300 , CL = 35 pF,Test Circuit 5; VS1 = 3 V/0 V, VS32 = 0 V/3V RL = 300 , CL = 35 pF; VS = 3 V, Test Circuit 6 RL = 300 , CL = 35 pF; VS = 3 V, Test Circuit 7 RL = 300 , CL = 35 pF; VS = 3 V, Test Circuit 8 VS = 0 V, RS = 0 , CL = 1 nF; Test Circuit 9 RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 11 RL = 50 , CL = 5 pF, Test Circuit 10 f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V Digital Inputs = 0 V or +5.5 V
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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REV. PrD
PRELIMINARY TECHNICAL DATA
SPECIFICATIONS
Parameter ANALOG SWITCH Analog Signal Range On-Resistance (R ON)
1(VDD = 3V 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
B Version -40C +25oC to +85C 0 V to VDD 6 11 12 0.4 1.2 3 Units V
ADG726/ADG732
Test Conditions/Comments
On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage I S (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH C IN, Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION
2
typ max typ max max typ max typ max typ max
VS = 0 V to VDD, IDS = 10 mA; Test Circuit 1 VS = 0 V to VDD , IDS = 10 mA VS = 0 V to VDD, IDS = 10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 2 VS = 1 V/3 V, VD = 3 V/1 V; Test Circuit 3 VS = VD = +1 V or +3 V; Test Circuit 4
0.01 1 0.01 1 0.01 1
5 5 10 2.0 0.8
nA nA nA nA nA nA
V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ pF typ pF typ pF typ pF typ pF typ A typ A max VIN = VINL or VINH
0.005 0.1 5 45 75 30 1 40 70 20 28 5 -60 -60 10 13 180 360 200 400 10 20
Break-Before-Make Time Delay, t D t ON(EN, WR) t OFF(EN) Charge Injection Off Isolation Channel to Channel Crosstalk -3 dB Bandwidth C S (OFF) C D (OFF) ADG726 ADG732 CD, CS (ON) ADG726 ADG732 POWER REQUIREMENTS IDD
RL = 300 , CL = 35 pF Test Circuit 5 VS1 = 2 V/0 V, VS32 = 0 V/2 V RL = 300 , CL = 35 pF; VS = 2 V, Test Circuit 6 RL = 300 , CL = 35 pF; VS = 2 V, Test Circuit 7 RL = 300 , CL = 35 pF; VS = 2 V, Test Circuit 8 VS = 0 V, RS = 0 , CL = 1 nF; Test Circuit 9 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 10 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 , CL = 5 pF, Test Circuit 10 f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz VDD = +3.3 V Digital Inputs = 0 V or +3.3 V
NOTES 1 Temperature ranges are as follows: B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
REV. PrD
-3-
PRELIMINARY TECHNICAL DATA
ADG726/ADG732-SPECIFICATIONS1 Dual Supply (V = +2.5 V 10%, V = -2.5 V 10%, GND = 0 V, unless otherwise noted)
DD SS
Parameter ANALOG SWITCH Analog Signal Range On-Resistance (R ON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage I S (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH C IN, Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION
2
B Version -40C +25oC to +85C VSS to VDD 3.5 5.5 6 0.3 0.8 1.2 0.01 1 0.01 1 0.01 1
Units V
Test Conditions/Comments
0.5
typ max typ max typ max typ max typ max typ max
VS = VSS to VDD, IDS = 10 mA; Test Circuit 1 VS = VSS to VDD, IDS = 10 mA VS = VSS to VDD, IDS = 10 mA VDD = +2.75 V, VSS = -2.75 V VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V; Test Circuit 2 VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V; Test Circuit 3 VS = VD = +2.25 V/-1.25 V, Test Circuit 4
5 5 10 1.7 0.7
nA nA nA nA nA nA
V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ pF typ pF typ pF typ pF typ pF typ A A A A typ max typ max VIN = VINL or VINH
0.005 0.1 5 40 60 15 1 32 50 16 26 8 -60 -60 10 13 180 360 200 400 10 20 10 20
Break-Before-Make Time Delay, t D t ON(EN, WR) t OFF(EN) Charge Injection Off Isolation Channel to Channel Crosstalk -3 dB Bandwidth C S (OFF) C D (OFF) ADG726 ADG732 CD, CS (ON) ADG726 ADG732 POWER REQUIREMENTS IDD ISS
RL = 300 , CL = 35 pF Test Circuit 5 VS1 = 1.5 V/0 V,VS32 = 0 V/1.5 V RL = 300 , CL = 35 pF; VS = 1.5 V, Test Circuit 6 RL = 300 , CL = 35 pF; VS = 1.5 V, Test Circuit 7 RL = 300 , CL = 35 pF; VS = 1.5 V, Test Circuit 8 VS = 0 V, RS = 0 , CL = 1 nF; Test 9 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 10 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 , CL = 5 pF, Test Circuit 10 f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz VDD = +2.75 V Digital Inputs = 0 V or +2.75 V VSS = -2.75 V Digital Inputs = 0 V or +2.75 V
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-4-
REV. PrD
PRELIMINARY TECHNICAL DATA ADG726/ADG732 TIMING CHARACTERISTICS1,2, 3
Parameter t1 t2 t3 t4 t5 t6 Limit at TMIN, TMAX 0 0 20 10 5 2 Units ns ns ns ns ns ns min min min min min min Conditions/Comments CS to WR Setup Time CS to WR Hold Time WR pulse width Time between WR cycles Address, Enable Setup Time Address, Enable Hold Time
NOTES 1 See Figure 1. 2 All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 Guaranteed by design and characterisation, not production tested. Specifications subject to change without notice.
CS t1 t3 WR t2 t4
t5 A0, A1, A2, A3, (A4) EN
t6
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. The ADG726 has two CS inputs. This enables the part to be used either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie CSA and CSB together.
REV. PrD
-5-
PRELIMINARY TECHNICAL DATA ADG726/ADG732
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to VSS VDD to GND VSS to GND Analog Inputs2
+7 V -0.3 V to +7 V +0.3 V to -7 V VSS - 0.3 V to VDD +0.3 Vor 30 mA, Whichever Occurs First Digital Inputs 2 -0.3V to VDD +0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D 60mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, S or D 30mA Operating Temperature Range Industrial (B Version) -40C to +85C
Storage Temperature Range -65C to +150C Junction Temperature +150C TBDC/W 48 lead CSP JA Thermal Impedance 48 lead TQFP JA Thermal Impedance TBDC/W Lead Temperature, Soldering (10seconds) 300C IR Reflow, Peak Temperature +220C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at A, WR, RS, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model ADG726BCP ADG726BSU ADG732BCP ADG732BSU
Temperature Range -40 -40 -40 -40
o o
Package Description Chip Thin Chip Thin Scale Quad Scale Quad Package (CSP) Flatpack Package (CSP) Flatpack
Package Option CP-48 SU-48 CP-48 SU-48
C C o C o C
to to to to
+85 +85 +85 +85
o o
C C o C o C
PIN CONFIGURATIONS CSP & TQFP
48 S13 47 S14 46 S15 45 S16 44 NC 43 D 42 NC 41 NC 40 S32 39 S31 38 S30 37 S29
48 S13A 47 S14A 46 S15A 45 S16A 44 NC 43 DA 42 NC 41 DB 40 S16B 39 S15B 38 S14B 37 S13B
S12 1 S11 2 S10 3 S9 4 S8 5 S7 6 S6 7 S5 8 S4 9 S3 10 S2 11 S1 12
PIN 1 INDICATOR
ADG732
TOP VIEW
36 S28 35 S27 34 S26 33 S25 32 S24 31 S23 30 S22 29 S21 28 S20 27 S19 26 S18 25 S17
S12A 1 S11A 2 S10A 3 S9A 4 S8A 5 S7A 6 S6A 7 S5A 8 S4A 9 S3A 10 S2A 11 S1A 12
PIN 1 INDICATOR
ADG726
TOP VIEW
36 S12B 35 S11B 34 S10B 33 S9B 32 S8B 31 S7B 30 S6B 29 S5B 28 S4B 27 S3B 26 S2B 25 S1B
VDD 13 VDD 14 A0 15 A1 16 A2 17 A3 18 A4 19 CS 20 WR 21 EN 22 GND 23 VSS 24
NC = NO CONNECT
NC = NO CONNECT
-6-
VDD 13 VDD 14 A0 15 A1 16 A2 17 A3 18 CSA 19 CSB 20 WR 21 EN 22 GND 23 VSS 24
REV. PrD
PRELIMINARY TECHNICAL DATA ADG726/ADG732
Table 1. ADG726 Truth Table
A3 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
E N CSA X X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSB 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WR L->H X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON Switch Retains previous switch condition No Change in Switch condition NONE S1A - DA, S1B - DB S2A - DA, S2B - DB S3A - DA, S3B - DB S4A - DA, S4B - DB S5A - DA, S5B - DB S6A - DA, S6B - DB S7A - DA, S7B - DB S8A - DA, S8B - DB S9A - DA, S9B - DB S10A - DA, S10B - DB S11A - DA, S11B - DB S12A - DA, S12B - DB S13A - DA, S13B - DB S14A - DA, S14B - DB S15A - DA, S15B - DB S16A - DA, S16B - DB
Table 2. ADG732 Truth Table
A4 X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A3 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
EN CS WR X X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L->H X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Switch Condition Retains previous switch condition No Change in Switch Condition NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -7-
X = Don't Care REV. PrD
PRELIMINARY TECHNICAL DATA ADG726/ADG732
TERMINOLOGY
VDD VSS IDD ISS GND S D IN VD (VS) RON R ON RFLAT(ON) I S (OFF) I D (OFF) ID, IS (ON) VINL VINH IINL(IINH) C S (OFF) C D (OFF) C D ,C S (ON) CIN tTRANSITION t ON(EN) t OFF(EN) tOPEN
Charge Injection Off Isolation A measure of unwanted signal coupling through an "OFF" switch. Crosstalk A measure of unwanted signal is coupled through from one channel to another as a result of parasitic capacitance. On Response The Frequency response of the "ON" switch. Insertion Loss The loss due to the ON resistance of the switch.
Most positive power supply potential. Most Negative power supply in a dual supply application. In single supply applications, connect to GND. Positive supply current. Negative supply current. Ground (0 V) reference. Source terminal. May be an input or output. Drain terminal. May be an input or output. Logic control input. Analog voltage on terminals D, S Ohmic resistance between D and S. On resistance match between any two channels, i.e. RONmax - RONmin Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea sured over the specified analog signal range. Source leakage current with the switch "OFF." Drain leakage current with the switch "OFF." Channel leakage current with the switch "ON." Maximum input voltage for logic "0". Minimum input voltage for logic "1". Input current of the digital input. "OFF" switch source capacitance. Measured with reference to ground. "OFF" switch drain capacitance. Measured with reference to ground. "ON" switch capacitance. Measured with reference to ground. Digital input capacitance. Delay time measured between the 50% and 90% points of the digital inputs and the switch "ON" condi tion when switching from one address state to another. Delay time between the 50% and 90% points of the EN digital input and the switch "ON" condition. Delay time between the 50% and 90% points of the EN digital input and the switch "OFF" condition. "OFF" time measured between the 80% points of both switches when switching from one address state to another. A measure of the glitch impulse transferred from the digital input to the analog output during switching.
-8-
REV. PrD
PRELIMINARY TECHNICAL DATA ADG726/ADG732 TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
TBD
TPC 1. On Resistance as a Function of VD(VS) for for Single Supply
TPC 4. On Resistance as a Function of VD(VS) for Different Temperatures, Single Supply
TPC 7. Leakage Currents as a function of VD(VS)
TBD
TBD
TBD
TPC 2. On Resistance as a Function of VD(VS) for Dual Supply
TPC 5. On Resistance as a Function of VD(VS) for Different Temperatures, Dual Supply
TPC 8. Leakage Currents as a function of VD(VS)
TBD
TBD
TBD
TPC 3. On Resistance as a Function of VD(VS) for Different Temperatures, Single Supply
TPC 6. Leakage Currents as a function of VD(VS)
TPC 9. Leakage Currents as a function of Temperature
REV. PrD
-9-
PRELIMINARY TECHNICAL DATA ADG726/ADG732
TBD
TBD
TBD
TPC 10. Leakage Currents as a Function of Temperature
TPC 13. TON/TOFF Times vs. Temperature
TPC 16. On Response vs. Frequency
TBD
TBD
TPC 11. Supply Currents vs. Input Switching Frequency
TPC 14. Off Isolation vs. Frequency
TBD
TBD
TPC 12. Charge Injection vs. Source Voltage
TPC 15. Crosstalk vs. Frequency
-10-
REV. PrD
PRELIMINARY TECHNICAL DATA ADG726/ADG732 Test Circuits
I DS
VDD
V1
VSS V SS
V DD S1
S D
S2 S32
D
ID (OFF)
A +0.8V
VS
VS
R O N = V 1/IDS
GND
EN
VD
Test Circuit 1. On Resistance.
VDD V DD S1 S2 VS VD S32 GND EN D +0.8V VSS V SS
Test Circuit 3. ID (OFF)
VDD V DD S1 S32 +2.4V VS GND EN VSS V SS D ID (ON) A VD
IS (OFF)
Test Circuit 2. IS (OFF).
VDD
VSS
Test Circuit 4. ID (ON)
3V
ADDRESS DRIVE (VIN )
0V
V DD A4
V SS S1
50%
50%
VS1
VIN
50
S2 THRU S31
A0
ADG732*
S32
VS32
VS1
D
EN CS GND WR
RL 300
CL 35pF
VOUT
90%
V OUT
VS32
90%
* SIMILAR CONNECTION FOR ADG726
tTRANSITION
tTRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION.
V DD VDD A4 VIN 50 A0
VSS VSS S1
3V ADDRESS DRIVE (VIN) 0V
VS
S2 THRU S31 ADG732* S32 D EN CS GND WR RL 300 CL 35pF VOUT
VS VOUT 80% 80%
t OPEN *SIMILAR CONNECTION FOR ADG726
Test Circuit 6. Break Before Make Delay, tOPEN.
REV. PrD
-11-
PRELIMINARY TECHNICAL DATA ADG726/ADG732
VDD VDD A4 VSS VSS S1 S2 THRU S32 A0 CS D VCS WR EN GND VWR *SIMILAR CONNECTION FOR ADG726 RL 300 CL 35pF VOUT SWITCH OUTPUT VO 0V tOFF (WR) 80% tON (WR) 20% ADG732* VS WR 0V 3V 50%
Test Circuit 7. Write Turn-On and Turn Off Time, tON , tOFF (WR).
VDD V DD
VSS VSS
S1 VS
A4
3V EN 0V tON (EN )
D RL 300 CL 35pF VOUT
50%
50%
S2 THRU S32 A0 ADG732*
tOFF (EN )
EN
VEN
CS GND WR
SWITCH OUTPUT
VO 0V
90%
10%
*SIMILAR CONNECTION FOR ADG726
Test Circuit 8. Enable Delay, tON(EN), tOFF(EN)
VDD V A4 DD VSS VSS 3V RS +2.4V LOGIC INPUT (VIN) 0V D CL 1nF VOUT V OUT QINJ = CL x VOUT VOUT
RS VS VIN
A0 S EN
ADG732*
*SIMILAR CONNECTION FOR ADG726
Test Circuit 9. Charge Injection.
VDD VSS A4 VDD VSS
VDD VSS A4 VDD VSS S1
NETWORK ANALYZER
50
NETWORK ANALYZER
A0
S1
ADG732* S32
S2
50
A0
VS
50
ADG732* S32
VS VOUT
EN**
D
RL 50
VOUT
D
EN CS GND WR
CS GND WR
RL 50
*SIMILAR CONNECTION FOR ADG726 ** CONNECT TO 2.4V FOR CROSSTALK MEASUREMENTS OFF ISOLATION = 20LOG10(VOUT/VS) INSERTION LOSS = 20LOG10 VOUT WITH SWITCH ( ) VOUT WITHOUT SWITCH
*SIMILAR CONNECTION FOR ADG726 CHANNEL TO CHANNEL CROSSTALK= 20LOG 10(VOUT /VS)
Test Circuit 10. OFF Isolation and Bandwidth.
Test Circuit 11. Channel-to-Channel Crosstalk.
-12-
REV. PrD
PRELIMINARY TECHNICAL DATA ADG726/ADG732
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead CSP (CP-48)
0.276(7.0) BSC SQ PIN 1 INDICATOR 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 37 0.009 (0.24)
36
0.010 (0.25) MIN
48 1
TOP VIEW
0.266 (6.75) BSC SQ
BOTTOM VIEW
0.207 (5.25) 0.201 (5.10) SQ 0.195 (4.95)
0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 12 MAX 0.035 (0.90) MAX 0.033 (0.85) NOM
o
25 24
12 13
0.217 (5.5) REF
0.028 (0.70) MAX 0.026 (0.65) NOM 0.002 (0.05) 0.0004 (0.01) 0.012 (0.30) 0.020 (0.50) 0.008(0.20) 0.0 (0.0) BSC 0.009 (0.23) REF 0.007 (0.18)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
48-Lead TQFP (SU-48)
0.047 (1.20) MAX 0.041 (1.05) 0.037 (0.95)
48 1
0.354 (9.00) BSC 0.276 (7.0) BSC
37 36
0.030 (0.75) 0.018 (0.45)
TOP VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05) 0 - 7 0 MIN 0.008 (0.20) 0.004 (0.09)
12 13
25 24
0.019 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
REV. PrD
-13-
0.354 (9.00) BSC
0.276 (7.0) BSC
SEATING PLANE

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Price & Availability of ADG726

	To Download ADG726 Datasheet File
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